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CDB61538 T50ACXX CMV3M 4ACT1 AN3001 D476A 1N959D 100HS
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  ve r s i o n 3 t o tal pages 19 date 2002.apr . 0 9 product specification 5.6  color tft-lcd module model name: a 0 5 6 d n 0 1 o r i g i n a l m o d e l n a m e : u p 0 5 6 d 0 1 ( ?.. ) preliminary specification (  ) final specification ? 2002 au optronics all rights reserved, do not copy . note: t h e co nt en t of t h i s sp ecifica t io n is su bjec t to change. www..net
record of revision version revise date page content 1 01/nov./1999 - first draft 2 11/se p ./2000 3 a.7. chan g e wei g ht (g) => ( 180 20 )  145 10 3.a. chan g e v glac of p ower su pp l y => ( 5 )( t yp . )  5 ( t yp . ) change v gldc of power supply => v gldc  v gl ? h change remark of v gl ? h => dc component of v gl  high level of v gl chan g e v cac of vcom => ( 5 )( t yp . )  5 ( t yp . ) change v cdc of vcom =>t b d (min.)  1.30( m i n .) tbd(typ.)  1.40(typ.) tbd (max.)  1.50(max.) 3.b. change i gh of current for driver =>(0.26)(typ.)  0.2(typ.) (0.8)(max.)  0.8(max.) change i gl of current for driver =>(-0.41)(typ.)  -0.5(typ.) (-1)(max.)  -1.0(max.) change i cc of current for driver =>(6.5)(typ.)  4.0(typ.) (12)(max.)  8.0(max.) change i dd of current for driver =>(10)(typ.)  12(typ.) (20)(max.)  20(max.) 6 change i vcom of current for driver =>tbd(typ.)  10(typ.) tbd (max.)  18(max.) 3.c. chan g e v l => tbd  - ( min. ) ( 580 )  470 ( t yp . ) ( 638 )  528 ( max. ) chan g e i l => ( 5 )  5.9 ( min. ) ( 7 )  6.1 ( max. ) chan g e f l => -  80 ( max. ) chan g e v s => ( 930 )  - ( t yp . ) remark: note 1,3,5 ( 1100 )  - ( t yp . ) remark: note 2,3,5 ( 1150 )  650 ( max. ) remark: note 1,3,5 ( 1150 )  910 ( max. ) remark: note 2,3,5 3 09/apr./2002 change the model name due to a new effective company_au www..net
pa g e : 1/19 contents: a. p h y s i c a l specificat i on .... ................................... p3 b . e l e c t r i c a l specificat i ons ... ................................... p4 1. pin assignment ........................................ p4 a . t ft-lcd panel driving section .......................................... p4 b . backlight d r i v i n g section .. ......................................... p5 2 . absolute max i m u m ratings ........................................... p5 3 . electrical characteristics ....................................... p6 a . t y pical operating conditions ......................................... p6 b . current consumption ........................................ p6 c. backlight driving conditions ........................................ p6 4. a c ti m i n g ........................................... p7 a . t i ming conditions ......................................... p7 b . t i ming diagram .......................................... p7 c . optical specifications ...................................... p8 d . reliability test items ........................................... p10 e . packing form ............................................ p1 1 all righ ts strictl y reser v ed . any por t ion of th is p a p e r shall no t be reprodu ced , copied , or transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 2/19 appendix: fig.1 outline dimension of tft-lcd module p12 fig.2 sampling clock timing p13 fig.3 horizontal display timing range p14 fig.4-(a) horizontal timing p15 fig.4-(b) detail horizontal timing p16 fig.5 v e rtical shift clock timing p17 fig.6-(a) v e rtical timing (from up to own) p18 fig.6-(b) v e rtical timing (from down to u p ) p19 all rights strictl y reser v ed . an y por t ion o f th is p a per shall no t be rep r o duced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 3/19 a. phy s ical specifications n o . i t e m s p e c i f i c a t i o n r e m a r k 1 d i s p l a y r e s o l u t i o n ( d o t ) 960(w) 2 3 4 ( h ) 2 a c t i v e a r e a ( m m ) 1 13.3(w) 8 4 . 7 ( h ) 3 s c r e e n s i z e ( i n c h ) 5 . 6 ( d i a g o n a l ) 4 d o t p i t c h ( m m ) 0.1 18(w) 0 . 3 6 2 ( h ) 5 color configuration r. g. b. stripe 6 o v e r a l l d i m e n s i o n ( m m ) 126.5(w) 100(h) 6 . 8 ( d ) n o t e 1 7 w e i g h t ( g ) 145 1 0 note 1: refer to fig. 1 pa g e : 4/19 all rights strictl y reser v ed . any por t ion of th is p a p e r shall no t be reprodu ced , copied , or transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
b. electrical specifications 1.pin assignment a. tft-lcd panel driving section pin no sy mbol i/o description remark 1 gnd - ground for logic circuit 2 v cc i supply voltage of logic control circuit for scan driver 3 v gl i negative power for scan driver 4 v gh i positive power for scan driver 5 stvr i/o v e rtical start pulse note 1 6 stvl i/o v e rtical start pulse note 1 7 ckv i shift clock input for scan driver 8 u/d i up/down scan control input note 1,2 9 oev i output enable input for scan driver 10 vcom i common electrode driving signal 1 1 vcom i common electrode driving signal 12 l/r i left/right scan control input note 1,2 13 q1h i analog signal rotate input 14 oeh i output enable input for data driver 15 sthl i/o start pulse for horizontal scan line note 1 16 sthr i/o start pulse for horizontal scan line note 1 17 cph3 i sampling and shifting clock pulse for data driver 18 cph2 i sampling and shifting clock pulse for data driver 19 cph1 i sampling and shifting clock pulse for data driver 2 0 v cc i supply voltage of logic control circuit for data driver 21 gnd - ground for logic circuit 22 vr i alternated video signal input(red) 23 vg i alternated video signal input(green) 24 vb i alternated video signal input(blue) 2 5 a v dd i supply voltage for analog circuit 2 6 a v ss - ground for analog circuit note 1: selection of scanning mode (please refer to the following table) all rights strictl y reser v ed . any por t ion of th is p a per shall no t be rep r odu ced , copi ed , o r tra ns f o rmed t o a n y o ther f o rm s w ith ou t p e rmi ss i on fr o m un ip a c o pt o ele c tr on i cs co rp . www..net
pa g e : 5/19 setting of scan control input in/out state for start pulse u / d l / r s t v r s t v l s t h r s t h l scanning direction g n d v cc o u t i n o u t i n from up to down, and from left to right. v cc g n d i n o u t i n o u t from down to up, and from right to left. g n d g n d o u t i n i n o u t from up to down, and from right to left. v cc v cc i n o u t o u t i n from down to up, and from left to right. in: input; out : output. note 2 : definition of scanning direction. refer to figure as below: b. backlight driving section( refer to fig. 1) f p c 1 26 right left up down n o . s y m b o l i / o d e s c r i p t i o n r e m a r k 1 hi i power supply for backlight unit (high voltage) 2 gnd - ground for backlight unit 2. absolute max i mum ratings i t e m s y m b o l c o n d i t i o n m i n . m a x . u n i t r e m a r k v cc g n d = 0 - 0 . 3 7 v av dd a v ss = 0 - 0 . 3 7 v v gh - 0 . 3 1 8 v v gl gnd=0 - 1 5 0 . 3 v power voltage v gh  v gl - 3 1 v v i - 0 . 3 a v dd + 0 . 3 v n o t e 1 v i - 0 . 3 v cc + 0 . 3 v n o t e 2 input signal voltage v c o m - 2 . 9 5 . 2 v operating temperature t o p a 0 6 0  ambient temperature storage temperature t s t g - 2 5 8 0  ambient temperature note 1: vr, vg, vb note 2: sthl, sthr, q1h, oeh, l/r, cph1~cph3, stvr, stvl, oev , ckv , u/d. all rights strictl y reser v ed . any por t ion of th is p a per shall no t be rep r odu ced , copi ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 6/19 3. electrical characteristics a. t y pical operating conditions (gnd=a v ss=0v , note 5 ) i t e m s y m b o l m i n . t y p . m a x . u n i t r e m a r k v cc 4 . 8 5 5 . 2 v av dd 4 . 8 5 5 . 2 v v gh 1 4 . 3 1 5 1 5 . 7 v v glac - 5 - v p - p ac component of v gl. note 1 power supply v gl h -10.5 -10 -9.5 v high level of v gl. v ia av s s + 0 .4 - a v dd - 0 . 4 v n o t e 2 v iac - 3 - v ac c o m p o n e n t v i deo signal amplitude (vr,vg,vb) v idc - a v dd / 2 - v dc component v cac - 5 - vp-p ac component,note 3 vcom v cdc 1 . 3 1 . 4 1 . 5 v dc c o m p o n e n t h level v ih 0 . 8 v cc - v cc v input signal volta g e l level v il 0 - 0.2v cc v note 4 note 1: the same phase and amplitude with common electrode driving signal(vcom). note 2: refer to fig.4-(a) note 3: t h e br ig htn e s s of lcd pan el cou l d b e adju s te d by the a d justment o f t h e a c compon e n t of vcom. note 4: sthl,sthr,q1h,oeh,l/r,cph1~cph3,stvr,stvl,oev , ckv , u/d. note 5: be sure to apply gnd, v cc and v gl to the lcd first, and then apply v gh . b. current consumption (gnd=a v ss=0v) p a r a m e t e r s y m b o l c o n d i t i o n m i n . t y p . m a x . u n i t r e m a r k i gh v gh = 1 5 v - 0 . 2 0 . 8 m a i gl v gl = - 1 0 v - - 0 . 5 - 1 m a i cc v cc = 5 v - 4 8 m a i dd a v dd = 5 v - 1 2 2 0 m a i vcom v cac =5v - 1 0 1 8 m a current for driver i l i 1 - - 1 0 - 1 0  a n o t e 1 note 1: logic input leakage current c. backlight driving conditions p a r a m e t e r s y m b o l m i n . t yp . m a x . u n i t r e m a r k lamp voltage v l - 4 7 0 5 2 8 v r m s n o t e 3 lamp current i l 5 . 9 6 6 . 1 m a r m s frequency f l - 6 0 8 0 k h z n o t e 3 , 4 - - 6 5 0 v r m s n o t e 1 , 3 , 5 lamp starting voltage v s - - 9 1 0 v r m s n o t e 2 , 3 , 5 note 1: t a = 25  . note 2: t a = 0  . note 3: reference value, correct value is subject to final backlight specification which will b e decided in the future. all rights strictl y reser v ed . any por t ion of th is p a per shall no t be rep r odu ced , copi ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 7/19 note 4: the lamp frequency should be selected as dif f erent as possible from display horizontal synchronous signal to avoid interference. note 5: for starting the backlig ht un it, the outpu t voltage of dc/ac? s transformer should be larg er than the maximum lamp starting voltage. 4. ac t i ming a. t i ming conditions p a r a m e t e r s y m b o l m i n . t y p . m a x . u n i t . r e m a r k rising time t r1 - - 6 0 n s c p h 1 ~ c p h 3 falling time t f1 - - 6 0 n s c p h 1 ~ c p h 3 rising time t r2 - - 1 2 0 n s c k v falling time t f2 - - 1 2 0 n s c k v high and low level pulse width t cph 1 5 0 1 5 4 1 5 8 n s c p h 1 ~ c p h 3 cph pulse duty t cw h 4 0 5 0 6 0 % c p h 1 ~ c p h 3 cph pulse delay t c12 t c23 t c31 3 0 t cph / 3 t cph / 2 n s c p h 1 ~ c p h 3 sth setup time t suh 2 0 - - n s s t h r , s t h l sth hold time t hdh 2 0 - - n s s t h r , s t h l sth pulse width t st h - 1 - t cph s t h r , s t h l sth period t h 6 1 . 5 6 3 . 5 6 5 . 5  s s t h r , s t h l oeh pulse width t oeh - 7 - t cph o e h sample and hold disable time t dis1 - 5 5 - t cph oev pulse width t oev - 2 7 - t cph o e v ckv pulse width t ckv - 4 1 - t cph c k v clean enable time t dis2 - 1 6 - t cph horizontal display start t sh - 0 - t cph / 3 horizontal display timing range t dh - 9 6 0 - t cph / 3 stv s e tup time t suv 4 0 0 - - n s s t v l , s t v r stv hold time t hdv 4 0 0 - - n s s t v l , s t v r stv pulse width t st v - - 1 t h s t v l , s t v r horizontal lines per field t v 2 5 6 2 6 2 2 6 8 t h n o t e 1 v e rtical display start t sv 3 - t h v e rtical display timing range t dv 2 3 4 - t h vcom rising time t rcom - 5  s vcom falling time t fcom - 5  s vcom delay time t dcom - 3  s rgb delay time t drgb - 1  s note 1: please don?t use odd horizontal lines to drive lcd panel for both odd and even field simultaneously . b. t i ming diagram please refer to the attached drawing, from fig.2 to fig.6. all righ ts strictl y reser v ed . any por t ion of this p a per shall no t be reprodu ced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 8/19 c. optical specification (note 1,note 2, note 3 ) i t e m s y m b o l c o n d i t i o n m i n . t y p . m a x . u n i t r e m a r k response time rise fall tr tf  =0 - - 15 20 30 40 ms ms note 4,6 contrast ratio cr at optimized viewing angle 1 0 0 1 5 0 - note 5,6 v i ewing angle t op bottom left right cr  10 10 30 45 45 - - - - - - - - deg . note 6,7 b r i g h t n e s s  =0 2 5 0 3 0 0 - n i t note 8 x  =0 0 . 2 5 0 . 3 0 0 . 3 5 whit e chromat i cit y y  =0 0 . 3 0 0 . 3 5 0 . 4 0 note 8 note 1. ambient temperature =25  . and lamp current i l = 6marms. note 2. t o be measured in the dark room. note 3. t o be me asur ed on the cen t e r a r ea of pa ne l with a v i ew ing con e o f 1 by t o p c on luminance meter bm-7, after 10 minutes operation. note 4. definition of response time: the o u t put sign als of p hot ode te ct o r are me asured w h e n t h e inp u t sig nals a r e ch ang e d from ?black? to ?white?(falling time)and from ?white? to ?black?(rising time),respectively . the re sp on se time is def in ed as the t i me interv al be t w een th e 10% an d 9 0 % o f amplitudes. refer to figure as below . "b l a c k " tr tf "w h i t e " "w h i t e " 0% 10 % 90 % 10 0 % s i g n a l ( r e l a t i v e v a l u e ) all righ ts strictl y reser v ed . any por t ion of th is p a er s hall no t be rep r oduced , copied, or transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 9/19 note 5. definition of contrast ratio: contrast ratio is calculated with the following formula. photodetector output when lcd is at ?white? state contrast ratio (cr)= photodetector output when lcd is at ?black? state note 6. white v i =v i50  1.5v black v i =v i50 2.0v ? ? means that the analog input signal swings in phase with com signal. ? ? means that the analog input signal swings out of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figure as below .  note 8. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened. all righ ts strictl y reser v ed . any por t ion of this p a p e r shall not be reprodu ced , cop i ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 10/19 d. reliability test items: n o . t e s t i t e m s c o n d i t i o n s r e m a r k 1 high temperature storage t a = 80  2 4 0 h r s 2 low temperature storage t a = -25  2 4 0 h r s 3 high temperature operation t a = 60  2 4 0 h r s 4 low temperature operation t a = 0  2 4 0 h r s 5 high temperature and high humidity t a = 60  , 95% rh 240hrs operation 6 h e a t s h o c k -25  ~80  /50 cycle 2hrs/cycle non-operation 7 e l e c t r o s t a t i c d i s c h a r g e 200v ,200pf(0  ), once for each terminal non-operation frequency range : 10~55hz s t o k e : 1 . 5 m m s w e e p : 1 0 ~ 5 5 h z ~ 1 0 h z 2 hours for each direction of x,y , z 8 v i b r a t i o n (6 hours for total) jis c7021, a-10 condition a 9 m e c h a n i c a l s h o c k 100g , 6ms, x, y, z 3 times for each direction jis c7021, a-7 condition c 10 v i bration (with carton) random vibration: 0.015g 2 /hz from 5~200hz ?6db/octave from 200~500hz iec 68-34 1 1 drop (with carton) height: (60)cm 1 corner , 3 ed g es , 6 surfaces jis z0202 note: t a : ambient temperature. all righ ts strictl y reser v ed . any por t ion of th is p a p e r shall no t be reprodu ced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 1 1 /19 e.packing form all righ ts strictl y reser v ed . any por t io n of this prp e r shall not be reprodu ced , cop i ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 12/19 (a ` n ?y J |v) fig. 1 outline dimensio of tft-lcd module all rig h ts stri ctl y reser v ed . any po r t ion of this p a p e r shall not be rep r odu ced , copied, o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 13/19 fig. 2 sampling clock timing 50 % 50 % 10 % 10 % 90 % 90 % sthl(r) cp h1 cph2 cp h3 st h t su h t t hd h c1 2 t t c3 1 t c2 3 cp h t t cwh t r f t all righ ts strictl y reser v ed . any por t ion of this p a per shall no t be reprodu ced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 14/19 fig. 3 horizontal display timing range input(sthl/sthr) output(sthr/sthl) cph1 t dh all rights strictl y reser v ed . any por t ion of th is p a p e r shall no t be reprodu ced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 15/19 fig.4-(a) horizontal timing oe h o ev vcom 1h t h v cdc cac v cac v v id c b l ank bla c k v ia v ia c wh i t e bla c k bla n k wh i t e (hsy) sthl(r) v ckv gl r(g b ) v all rig h ts stri ctl y reser v ed . any po r t ion of this p a p e r shall not be rep r odu ced , copied, o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 16/19 oe h oe v vcom (hsy) sthl(r) v ckv gl r( gb) v 1h t di s2 oe h t t di s1 t sth t oe v t ck v t fc o m 10 % 90 % 90 % 10 % 10 % 90 % 50 % 50 % 10 % 90 % t dc om t rc om t dr gb note: the falling edge of oev should be synchroni zed with the falling edg e of oeh fig. 4-(b) detail horizontal timing all righ ts strictl y reser v ed . any por t ion of this p a per shall no t be reprodu ced , copied , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 17/19 fig.5 v e rtical shift clock timing stvr(l) ckv 50 % 50 % t su v hd v t t ck v all rig h ts stri ctl y reser v ed . any po r t ion of this p a p e r shall not be rep r odu ced , copied, o r tran s f o rmed t o any o ther f o rm s w ith ou t p e rmi ss i o n fr o m u nip a c o pt o ele c tr o ni cs co rp . www..net
pa g e : 18/19 fig.6-(a) v e rtical timing (from up to down) vcom(eve n fi eld) vcom(odd field ) stvl (vsy) displa y on panel f i rs t lin e v r(gb ) (h sy) t sv all rights strictl y reser v ed . any por t ion of th is p a per shall no t be rep r odu ced , copi ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net
pa g e : 19/19 fig.6-(b) v e rtical timing (from down to up) vc om (e v e n fi eld) st vr (v sy) disp lay on p anel fi rst l i n e v r( g b ) (h sy) t sv vc om (o dd fie l d) all rights strictl y reser v ed . any por t ion of th is p a per shall no t be rep r odu ced , copi ed , o r transformed t o any other forms without pe rmission from unip a c opt o electronics corp . www..net


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